The present disclosure relates to standard cells effective in reducing manufacturing defects of via contacts, standard cell libraries, and layout structures of semiconductor integrated circuits.
First, definitions of terms used in the specification are provided below. The term “dummy metal interconnect” refers to a metal interconnect other than metal interconnects which are not dummy. As to the term “metal interconnect which is not dummy,” if a circuit can no longer accomplish preferable logic operation when the entire region of a metal interconnect is removed to break the connection to a layer under or over a via contact connected to the metal interconnect, the metal interconnect is defined as a metal interconnect which is not dummy. Note that in the specification, a metal interconnect which is not dummy is simply referred to as a “metal interconnect.”
The term “dummy via contact” refers to a via contact which is not connected to a metal interconnect other than dummy metal interconnects. The presence or absence of a dummy via contact is irrelevant to accomplishment of preferable logic operation of a circuit.
The term “gate interconnect” refers to an interconnect on a shallow trench isolation (STI) region, where the gate interconnect is formed in the same layer as that of the gate of a transistor made of, for example, polysilicon, is made of the same material as that of the gate of the transistor, and is connected to the gate of the transistor in the same layer.
The term “active gate” refers to a concept including a gate of a transistor and a gate interconnect in combination.
The term “dummy gate” refers to an interconnect on a shallow trench isolation region, where the interconnect is formed in the same layer as that of an active gate, is made of the same material as that of the active gate, but is not connected to the active gate in the same layer.
The term “gate region” refers to a concept including an active gate and a dummy gate in combination.
The term “off transistor” refers to a transistor kept in an off state in which the gate potential of a p-channel transistor is fixed at a power supply potential, or the gate potential of an n-channel transistor is fixed at a ground potential.
Generally, variations in the density of via contacts closely relate to manufacturing defects of the via contacts. The manufacturing defects of the via contacts are one of causes reducing the fabrication yield of semiconductor integrated circuits. Thus, various methods to overcome the above problems have been proposed. For example, in Japanese Patent Publication No. H6-85080, as a portion of a chip where via contacts are sparsely distributed, attention is focused on a shallow trench isolation region where no transistors are disposed. Dummy via contacts are disposed on the shallow trench isolation region to eliminate the non-uniformity in distribution of disposition of the via contacts. Moreover, Japanese Patent Publication No. 2007-129030 describes a configuration in which a dummy via contact having the same potential as that of a via contact is disposed through shared use of a lower layer to which the via contact is connected.